A Flipchip in Leaded Molded Package (FLMP) is described in U.S. patent application Ser. No. 09/464,717. In a conventional FLMP package, the backside of a silicon die is exposed through a window in a molding material. The backside of the die can be in substantially direct thermal and electrical contact with a circuit substrate such as a PC board.
When the FLMP package is made, a molding process is performed after the die is attached to a leadframe structure. To keep the backside of the die clean from mold bleed or mold flash, the package is designed so that no gap is present between the mold cavity and the backside of silicon die. During manufacture, the die is contacted by a mold tool upon mold tool clamping. Since the die is brittle and since the package is thin, the potential for breakage of the die and disconnection between the die and the leadframe is of concern.
Embodiments of the invention address these and other problems.